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1 n io-link ? phy compatible (com1/com2/com3) n cable interface protected to 60v n operation from 7.5v to 40v n integrated step-down switching regulator n max load current: 100ma (lt3669)/ 300ma (LT3669-2) n synchronizable and adjustable switching frequency: 250khz to 2.2mhz n output voltage: 0.8v to 16v n integrated 150ma ldo linear regulator n rugged line drivers with adjustable slew rate and current limit n adaptive line driver pulsing scheme to switch heav y loads safely n drivers configurable as push-pull, pull-up or pull-down n adjustable power-on reset timer n small 28-pin thermally enhanced 4mm 5mm qfn package typical a pplica t ion fea t ures descrip t ion io-link transceiver with integrated step-down regulator and ldo the lt ? 3669 is an industrial transceiver that includes a step-down switching regulator and a low dropout linear regulator. wake-up detect functionality, as well as a pro - grammable power-on reset timer are also included. the current limit and slew rate of the transmitters are externally adjustable for optimum emc performance. the line drivers can source/sink up to 250 ma of current each or 500 ma when connected together, with a minimal residual voltage of less than 2.1 v. an internal adaptive pulsing scheme allows the drivers to safely switch heavy capacitive loads and incandescent bulbs. thermal shut - down provides additional protection. line protection of 60v in the line interface pins allows the use of standard tvs diodes with l+ operating voltages up to 40v. the switching regulator integrates the catch diode in lt3669 ( up to 100 ma load current) and requires an exter - nal catch diode in lt3669 -2 ( up to 300 ma load current). the lt3669 implements an io- link device phy. for io- link master designs, see the ltc2874. operating waveforms a pplica t ions n industrial sensors and actuators l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. io-link is a registered trademark of profibus user organization (pno). all other trademarks are the property of their respective owners. rst sc1 sc2 wake rxd1 txen1 txd1 txen2 txd2 reset i/o i/o i/o i/o i/o i/o i/o i/o dio en/uvlo l+ q2 cq1 agnd fb ldo ldo ilim 36692 ta01a c gnd bst sync sr bd ldo in sw fb out rt cpor 250ma 250ma 2 3 1 4 0.1f 5v 100ma 10f 3.3v 100ma v l+ , 7.5v to 40v transient to 60v lt3669 1f t rst = 12.5ms f sw = 600khz 0.1f 82h 38.3k 42.2k 53.6k 14k 4.42k 470pf 10.2k 470pf 4.7f 10s/div txd1 5v/div rxd1 5v/div (rxd1 pull-up resistor = 10k) cq1 5v/div 0v 0v 0v 36692 ta01b lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
2 a bsolu t e maxi m u m r a t ings l +, en / uvlo voltage ( note 3) .................... C 60 v to 60 v cq 1, q2 voltage .......................................... C 60 v to 60 v (l+ to cq 1), ( l+ to q 2) voltage ................... C 60 v to 60 v dio , ldo in voltage ( note 3) ...................... C 0.3 v to 60 v dio above l+ voltage ............................................... 90 v bs t voltage .............................................................. 50 v bs t above sw voltage ............................................. 30 v bd voltage ................................................................ 30 v l do voltage ................................................................ 8 v ldo above ldo in voltage ....................................... 0. 3 v (notes 1 and 2) p in c on f igura t ion fb out , fb ldo , sync voltage ....................................... 6 v cpor , rt, ilim voltage .............................................. 3 v sr , txen 1, txd 1, txen 2, txd 2 voltage ................. 30 v s c1 , sc2 , wake , rst , rxd 1 voltage ....................... 30 v o perating junction temperature range ( n otes 4 and 5) lt 36 69 e ............................................ C4 0 c to 125 c lt 36 69 i ............................................. C 40 c to 125 c lt 36 69 h ............................................ C 40 c to 150 c storage temperature range .................. C 65 c to 150 c lt3669 LT3669-2 9 10 top view ufd package 28-lead (4mm 5mm) plastic qfn 29 gnd 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 sc1 sc2 wake rxd1 txen1 txd1 txen2 txd2 rt fb out fb ldo ldo ldo in bd bst sw rst cpor ilim sr sync agnd q2 cq1 l+ en/uvlo dio gnd 7 17 18 19 20 21 22 16 8 15 ja = 44c/w, jc = 8c/w exposed pad ( pin 29) is gnd, must be soldered to pcb 9 10 top view ufd package 28-lead (4mm 5mm) plastic qfn 29 gnd 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 sc1 sc2 wake rxd1 txen1 txd1 txen2 txd2 rt fb out fb ldo ldo ldo in bd bst sw rst cpor ilim sr sync agnd q2 cq1 l+ en/uvlo dio da 7 17 18 19 20 21 22 16 8 15 ja = 44c/w, jc = 8c/w exposed pad ( pin 29) is gnd, must be soldered to pcb lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v l+ = 24v, v en/uvlo = 24v. (note 4) symbol parameter conditions min typ max units power supply l+ undervoltage lockout threshold v l+ rising l 6.4 7.5 v v ovth l+ overvoltage lockout threshold v l+ rising l 40.5 43 45 v shutdown current from l+ v en/uvlo = 0.4v 1.15 1.65 ma quiescent current from l+ not switching 4 6 ma switching regulator v fbout switching regulator feedback voltage l 777 794 811 mv fb out pin bias current fb out pin voltage = 800mv l C15 C100 na fb out voltage line regulation 7.5v < v l+ < 40v 0.005 %/v switching frequency r t = 5.36k r t = 19.1k r t = 107k 1.94 0.88 219 2.28 1.04 258 2.62 1.20 297 mhz mhz khz minimum switch off-t ime r t = 19.1k l 130 210 ns foldback frequency r t = 19.1k, fb out = 0v 115 khz switch current limit (note 6) lt3669 LT3669-2 l l 240 480 325 650 410 820 ma ma switch v cesat (v dio C v sw ) i sw = C100ma (lt3669) i sw = C300ma (LT3669-2) 330 550 mv mv switch leakage current 0.01 2 a catch schottky diode forward voltage drop i sw = C100ma (lt3669) 720 mv catch schottky diode current limit to stop internal oscillator lt3669 LT3669-2 140 330 200 450 260 570 ma ma reverse protection diode for ward voltage drop i dio = C100ma (lt3669) i dio = C300ma (LT3669-2) 720 840 mv mv reverse protection diode reverse leakage 0.01 2 a boost schottky diode forward voltage drop i bst = C6ma (lt3669) i bst = C15ma (LT3669-2) 700 750 mv mv boost schottky diode reverse leakage v bst C v bd = 24v 0.01 2 a minimum bst voltage (note 7) 1.4 1.8 v o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3669eufd#pbf lt3669eufd#trpbf 3669 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3669iufd#pbf lt3669iufd#trpbf 3669 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3669hufd#pbf lt3669hufd#trpbf 3669 28-lead (4mm 5mm) plastic qfn C40c to 150c lt3669eufd-2#pbf lt3669eufd-2#trpbf 36692 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3669iufd-2#pbf lt3669iufd-2#trpbf 36692 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3669hufd-2#pbf lt3669hufd-2#trpbf 36692 28-lead (4mm 5mm) plastic qfn C40c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
4 symbol parameter conditions min typ max units bst pin current i sw = C100ma (lt3669) i sw = C300ma (LT3669-2) 5.25 10.5 7.5 15 ma ma sync threshold v oltage 0.5 0.9 1.5 v sync input frequency 0.3 2.2 mhz en/uvlo threshold voltage v en/uvlo rising l 1.44 1.5 1.56 v en/uvlo pin hysteresis l 50 75 100 mv ldo linear regulator v fbldo ldo feedback voltage l 777 794 811 mv fb ldo pin bias current fb ldo pin voltage = 800mv l C20 C100 na fb ldo voltage line regulation 7.5v < v l+ < 40v, v l+ C v ldo > 4v 0.005 %/v ldo current limit l 151 180 235 ma ldo current limit foldback v ldoin = 40v, v ldo = 0v l 15 35 55 ma ldo dropout voltage ldo load current = 25ma ldo load current = 150ma l 60 340 90 mv mv ldo minimum load current l 150 175 a power-on reset v rstth reset threshold as % of v fbout (v fbldo ) fb out (fb ldo ) pin voltage falling (figure 6) l 90.4 92.7 95 % t rst reset timeout period c por = 100nf, rst r pu = 100k (figure 6) l 10 12.5 15 ms t uv uv detect to rst asserted step v fbout (v fbldo ) from 0.9v to 0.5v, rst r pu = 100k (figure 6) l 11 24 37 s line driver thermal shutdown thermal shutdown threshold (note 8) junction temperature t j increasing 125 140 155 c thermal shutdown threshold (note 8) junction temperature t j decreasing 111 128 135 c thermal shutdown hysteresis (note 8) 10 12 14 c line drivers i qh dc driver current p-switching output (on state) v ilim 0.3v, 7.5v < v l+ < 40v r ilim = 42.2k, 7.5v < v l+ < 40v l l 105 280 140 330 190 420 ma ma i ql dc driver current n-switching output (on state) v ilim 0.3v, 7.5v < v l+ < 40v r ilim = 42.2k, 7.5v < v l+ < 40v l l 105 280 140 330 190 420 ma ma v rqh residual voltage high (v l+ to v cq1,q2 ) i cq1,q2 = C100ma i cq1,q2 = C250ma l l 1.15 1.5 1.65 2.1 v v v rql residual voltage low (v cq1,q2 ) i cq1,q2 = 100ma i cq1,q2 = 250ma l l 1.15 1.5 1.65 2.1 v v v rqh (v rql ) pulsing threshold v rqh (v rql ) increasing 2.7 2.95 3.2 v v rqh (v rql ) pulsing threshold hysteresis 20 50 80 mv cq1, q2 pin leakage current C40c to 125c, v txenn < 0.4v C40c to 150c, v txenn < 0.4v l l 1.2 1.2 3 8 a a receiver v thh input threshold h v l+ > 18v (figure 14) l 10.5 11.8 13 v v thl input threshold l v l+ > 18v (figure 14) l 8.0 9.6 11.2 v v hys input hysteresis v l+ > 18v (figure 14) l 1.8 2.2 2.6 v e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v l+ = 24v, v en/uvlo = 24v. (note 4) lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
5 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v l+ = 24v, v en/uvlo = 24v. (note 4) e lec t rical c harac t eris t ics s wi t ching c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v l+ = 24v, v en/uvlo = 24v. (note 4) symbol parameter conditions min typ max units driver and receiver f dtr maximum data transfer rate c cq1,q2 4nf v sr 0.4v (for com1/com2) v sr 0.9v (for com3) l l 38.4 230.4 kb/s kb/s t bit bit time v sr 0.4v (for com2) v sr 0.9v (for com3) 26.04 4.34 s s driver t dr rise time c cq1,q2 4nf (figure 1) v sr 0.4v (for com1/com2) v sr 0.9v (for com3) l l 1.6 0.26 5.2 0.869 s s t df fall time c cq1,q2 4nf (figure 1) v sr 0.4v (for com1/com2) v sr 0.9v (for com3) l l 2.1 0.34 5.2 0.869 s s t phld , t plhd propagation delay c cq1,q2 4nf (figure 2) v sr 0.4v (for com1/com2) v sr 0.9v (for com3) l l 3.3 0.72 6 1.3 s s t skewd skew t skewd = |t phld C t plhd |, c cq1,q2 4nf (figure 2) v sr 0.4v (for com1/com2) v sr 0.9v (for com3) l l 0.25 140 1.5 400 s ns t zhd , t zld enable time c cq1,q2 = 100pf, r pu = r pd = 10k (figure 3) v sr 0.4v (for com1/com2) v sr 0.9v (for com3) l l 3.4 0.8 6.1 1.4 s s t hzd , t lzd disable time c cq1,q2 = 100pf, r pu = r pd = 10k (figure 3) v sr 0.4v (for com1/com2) v sr 0.9v (for com3) l l 4 4 6 6 s s t dwu minimum wake-up pulse duration to be acknowledged r pu = r pd = 10k (figure 7) wake pull-up resistor = 5k l 55 75 s t lzw delay from handshake sequence finished to wake high (note 9) wake pull-up resistor = 5k 0.3 1 s pulsing on-time v rqh (v rql ) = 24v, only cq1 or q2 pulsing 320 s pulsing off-time 2.2 ms symbol parameter conditions min typ max units digital io wake , rxd1, scn pull-down output current if asserted v scn = v wake = v rxd1 = 0.3v l 0.7 1.05 ma rst pull-down output current if asserted v rst = 0.3v l 0.2 0.3 ma v ih txdn, txenn, sr input high voltage l 0.9 v v il txdn, txenn, sr input low voltage l 0.4 v i lk txdn, txenn, sr pin input leakage current 0.1 1 a c in txdn, txenn, sr pin input capacitance 2.5 pf lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
6 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v l+ = 24v, v en/uvlo = 24v. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to gnd. all currents into device pins are positive; all currents out of device pins are negative. note 3: absolute maximum voltage at l+, en/uvlo, dio and ldo in pins is 60v for non-repetitive one second transients, and 40v for continuous operation. note 4: the lt3669e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3669i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3669h is guaranteed over the full C40c to 150c operating junction temperature range. specifications for the line driver do not apply above the thermal shutdown temperature. note 5: this ic includes overtemperature protection that is intended to protect the device during momentar y overload conditions and will shut the line drivers off for typical junction temperatures higher than 140c. the ldo and switching regulator will shut off for typical junction temperatures higher than 168c. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 6: current limit guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycles. note 7: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the npn power switch. note 8: thermal shutdown guaranteed by design and/or correlation to static test. note 9: handshake sequence: set txen1 low and then toggle txd1. s wi t ching c harac t eris t ics symbol parameter conditions min typ max units receiver noise suppression time v sr 0.4v (for com1/com2) (figure 5) v sr 0.9v (for com3) (figure 5) l l 1/16 1/16 3.5/16 5/16 t bit t bit t phlr , t plhr propagation delay rxd1 pull-up resistor = 5k (figure 4) v sr 0.4v (for com1/com2) v sr 0.9v (for com3) l l 4.6 1.45 6.5 2.1 s s t skewr receiver skew t skewr = |t phlr C t plhr |, rxd1 r pu = 5k ( figure 4) v sr 0.4v (for com1/com2) v sr 0.9v (for com3) l l 0.5 100 1.5 400 s ns c cqi cq1 pin input capacitance 20 pf lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
7 temperature (c) ?50 0 50 75 ?25 25 125100 150 36692 g02 feedback voltage (mv) 780 800 790 785 805 795 810 temperature (c) feedback voltage (mv) 780 800 790 785 805 795 810 36692 g01 ?50 0 50 75 ?25 25 125100 150 temperature (c) ?50 ovlo (v) 0 50 75 41.0 43.0 42.0 41.5 43.5 42.5 44.5 44.0 ?25 25 125100 150 36692 g04 v l+ rising v l+ falling temperature (c) ?50 en/uvlo pin threshold (v) 0 50 75 1.30 1.50 1.40 1.35 1.55 1.45 1.60 ?25 25 125100 150 36692 g03 en/uvlo rising en/uvlo falling uvlo (v) 5.0 6.0 7.0 5.5 6.5 7.5 temperature (c) ?50 0 50 75 ?25 25 125100 150 36692 g05 v l+ rising v l+ falling 0 l+ supply current (ma) 10 15 0 0.8 0.4 0.2 1.0 0.6 1.4 1.2 5 2520 30 35 40 36692 g06 v l+ (v) v l+ = 24v 0 l+ supply current (ma) 0.4 0.8 1.2 1.4 0.2 0.6 1.0 temperature (c) 36692 g07 ?50 0 50 75 ?25 25 125100 150 typical p er f or m ance c harac t eris t ics l+ overvoltage lockout l+ undervoltage lockout l+ supply current, v en/uvlo < 0.4v l+ supply current, v en/uvlo < 0.4v no-load l+ supply current, v en/uvlo = v l+ no-load l+ supply current, v en/uvlo = v l+ , v txen2 = 0v fb out feedback voltage fb ldo feedback voltage en/uvlo pin threshold l+ supply current (ma) 0 2 4 1 3 5 temperature (c) 36692 g08 th erma l s hut do wn f ron t pa ge app li ca tion v l+ = 24v v txen = 0v ?50 0 50 75 ?25 25 125100 150 l+ supply current (ma) 10 15 2 6 4 3 7 5 9 8 5 2520 30 35 40 36692 g09 v l+ (v) v txen1 = 5v, v txd1 = 0v v txen1 = 5v, v txd1 = 5v v txen1 = 0v lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
8 0 switch voltage drop, v cesat (mv) 100 150 300 100 0 400 200 350 150 50 250 450 50 250200 300 36692 g15 switch current (ma) 12.0 reset timeout period, t rst (ms) 12.4 12.6 12.8 13.0 12.3 12.2 12.1 12.5 12.7 12.9 temperature (c) 36692 g11 c por = 100nf ?50 0 50 75 ?25 25 125100 150 cpor pin capacitance, c por (nf) reset timeout period, t rst (ms) 0.1 1 10 100 1000 10000 0.01 0.1 1 100 10 0.01 1000 36692 g12 duty cycle (%) 0 switch current limit (ma) 400 500 600 70 300 200 20 40 10 90 30 50 80 60 100 100 0 700 36692 g13 LT3669-2 lt3669 0 bst pin current (ma) 100 150 6 2 0 8 4 7 3 1 9 5 10 50 250200 300 36692 g16 switch current (ma) typical p er f or m ance c harac t eris t ics switch current limit switch current limits switch voltage drop bst pin current boost diode forward voltage reverse-protection diode forward voltage power-on reset threshold reset timeout period reset timeout period temperature (c) por threshold (%) 91.0 93.0 92.0 91.5 93.5 92.5 94.o 36692 g10 fb out fb ldo ?50 0 50 75 ?25 25 125100 150 400 500 600 300 200 100 0 700 switch current limit (ma) temperature (c) 36692 g14 c urr ent limit dc = 0% c urr ent limit dc = 100% ca tch di od e c urr ent limit LT3669-2 lt3669 ?50 0 50 75 ?25 25 125100 150 boost diode current (ma) 0 0.8 1.0 0.6 0.4 100 50 150 200 0.2 0 1.2 boost diode forward voltage (v) 36692 g17 diode current (ma) 0 0 reverse-protection diode v f (v) 0.2 0.4 0.6 50 100 150 200 250 0.8 1.0 0.1 0.3 0.5 0.7 0.9 300 36692 g18 lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
9 v l+ = 24v r t = 38.3k frequency (khz) 580 600 620 570 590 610 630 temperature (c) 36692 g19 ?50 0 50 75 ?25 25 125100 150 0 switching frequency (khz) 40 60 1400 600 200 1800 1000 1600 800 400 2000 1200 2200 20 10080 120 36692 g20 r t (k) buck load current (ma) 300 100 0 400 200 350 150 50 450 250 500 36692 g23 5 15 20 10 30 35 25 40 v l+ (v) t ypi cal minimum LT3669-2, l = 33h lt3669, l = 82h f = 600 khz dio pin floating 0 efficiency (%) 100 150 75 35 15 55 85 45 25 65 95 50 250200 300 36692 g24 buck load current (ma) all lt3669 current included f = 600khz, v txen = 0v, v ilim = 0v dio pin floating 12v 24v 36v lt3669 v l+ : 12v 24v 36v LT3669-2 v l+ : 0 efficiency (%) 100 150 70 30 10 50 80 40 20 60 90 50 250200 300 36692 g27 buck load current (ma) all lt3669 current included f = 400khz, v txen = 0v, v ilim = 0v dio pin floating 12v 24v 36v lt3669 v l+ : 12v 24v 36v LT3669-2 v l+ : typical p er f or m ance c harac t eris t ics minimum switch-on time/ switch off-time maximum buck output current, v out = 5v efficiency, v out = 5v catch diode forward voltage (lt3669 only) maximum buck output current, v out = 3.3v efficiency, v out = 3.3v switching frequency switching frequency frequency foldback 0 switching frequency (khz) 200 300 0 400 200 100 500 300 700 600 100 500400 600 700 800 36692 g21 fb out pin voltage (mv) r t = 38.3k switch on -time/switch o ff -time (ns) temperature (c) ?50 0 50 75 ?25 25 125100 150 36692 g22 minimum o ff -time minimum on -time bu ck load c urr ent = 150 ma 120 40 0 160 80 140 60 20 100 180 buck load current (ma) 300 100 0 400 200 350 150 50 450 250 500 36692 g25 5 15 20 10 30 35 25 40 v l+ (v) t ypi cal minimum LT3669-2, l = 33h lt3669, l = 82h f = 400 khz dio pin floating catch diode current (ma) 0 catch diode forward voltage (v) 0.4 0.5 0.7 0.6 70 0.3 0.2 20 40 10 90 30 50 80 60 100 0.1 0 0.8 36692 g25 lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
10 0 dropout voltage, v ldoin ? v ldo (mv) 100 200 300 400 50 150 250 350 i load = 150ma i load = 30ma temperature (c) ?50 0 50 75 ?25 25 125100 150 36692 g30 ldo current limit (ma) v l+ = 24v temperature (c) 36692 g31 140 60 20 180 100 160 80 40 220 200 120 v ldoin ? v ldo = 5v v ldoin ? v ldo = 24v v ldoin ? v ldo = 30v v ldoin ? v ldo = 40v ?50 0 50 75 ?25 25 125100 150 0 ldo current limit (ma) 10 15 140 60 20 180 100 160 80 40 200 120 5 25 30 35 20 40 36692 g32 v ldoin ? v ldo (v) temperature (c) ?50 ldo minimum load current (a) 0 50 75 100 150 350 250 200 400 300 450 ?25 25 125100 150 36692 g33 v ldo = 300mv v ldo = 400mv v ldo = 500mv v ldo = 600mv v ldo = 700mv typical p er f or m ance c harac t eris t ics ldo current limit foldback ldo minimum load current ldo load regulation ldo load transient response ldo dropout voltage buck load regulation buck load transient response ldo current limit 100s/div v ldo 100mv/div i ldo 100ma/div 5ma 36692 g35 v ldo = 3.3v c ldo = 1f 0 36692 g28 ?1 .0 ?0 .8 ?0 .6 ?0 .4 ?0 .2 0.2 0.4 0.6 0.8 1.0 load re gu lati on (%) 0 50 100 150 200 250 300 bu ck load c urr ent (ma) lt3669 front page application referenced to v out at 50ma load LT3669-2 f = 600khz, l = 33h referenced to v out at 150ma load 36692 g29 v out = 5v v out = 5v i out 200 ma/div 20 ma v out 200 mv/div i out 200 ma/div 10 ma v out 200 mv/div 100 s/div LT3669-2 c out = 22f f = 600khz, l = 33h lt3669 front page application 36692 g34 load re gu lati on (%) 0 25 50 75 10 0 125 15 0 ldo load c urr ent (ma) referenced to v ldo at 0ma load ?0 .10 ?0 .09 ?0 .08 ?0 .07 ?0 .06 ?0 .05 ?0 .04 ?0 .03 ?0 .02 ?0 .01 0 lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
11 typical p er f or m ance c harac t eris t ics line driver current limit cq1, q2 pin leakage current v txen < 0.4v line driver pulsing on-time/ off-time line driver pulsing on-time/ off-time line driver output waveforms line driver residual voltage line driver residual voltage receiver thresholds receiver thresholds temperature (c) ?50 receiver thresholds (v) 0 50 75 2 6 4 10 12 8 3 7 5 11 13 9 ?25 25 125100 150 36692 g36 v thh v thl 5 receiver thresholds (v) 15 25 30 2 6 4 10 12 8 3 7 5 11 13 9 10 20 35 40 36692 g37 v thh v thl v l+ (v) temperature (c) ?50 cq1, q2 pin leakage current (a) 0 50 75 0.5 1.0 3.0 2.0 1.5 3.5 2.5 4.0 ?25 25 125100 150 36692 g38 18v 24v 30v 40v v l+ : 0 line drivers current limit (ma) 100 200 300 400 50 150 250 350 r ilim = 42.2k v ilim 0.3v temperature (c) ?50 0 50 75 ?25 25 125100 150 36692 g39 temperature (c) ?50 residual voltage (v) 0 50 75 0.6 1.4 1.0 0.8 1.6 1.2 1.8 ?25 25 125100 150 36692 g40 v rqh v rql i q = 250ma i q = 100ma 36692 g41 v rql v rqh 0 25 50 75 100 125 150 175 200 225 250 line dr iver s our ce/sink c urr ent (ma) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 resi du al vo lt age (v) temperature (c) 36692 g42 pulsing on-time, v rqh,l = 40v pulsing on-time, v rqh,l = 24v pulsing on-time, v rqh,l = 5v pulsing off-time 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 pulsi ng on -time / o ff -time (ms) ?50 0 50 75 ?25 25 125100 150 0 10 20 25 40 5 15 30 35 residual voltage, v rqh,l (v) 36692 g43 pulsing not occurring below 3v pulsing on-time pulsing off-time 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 pulsi ng on -time / o ff -time (ms) 36692 g44 0v 0v 0v v txd1 5v/div v rxtd1 5v/div v cq1 5v/div v sr > 0.9v, rxd1 pull-up resistor = 10k 2 s/div lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
12 p in func t ions sc1 (pin 1): cq1 short-circuit detect open-collector output. sc 1 pulls low when a short-circuit is detected on the cq1 driver output or after a thermal shutdown event. use a 100 k pull-up resistor to the cs supply. lowpass filter this signal before further processing. see the ap - plications information section. sc 2 ( pin 2): q 2 short - circuit detect open- collector output. sc 2 pulls low when a short-circuit is detected on the q2 driver output or after a thermal shutdown event. use a 100 k pull-up resistor to the cs supply. lowpass filter this signal before further processing. see the ap - plications information section. w ake (pin 3): wake-up detect open-collector output. wake pulls low when driver 1 detects a wake-up pulse longer than 75 s at the cq1 pin ( indicating that a data transmission is beginning). wake returns to high imped - ance after the handshaking sequence of setting txen1 low and then toggling txd1 or after an internal reset event. use a 10k pull-up resistor to the cs supply. rxd1 (pin 4): cq1 receiver output, open collector. use a pull-up resistor of 10 k or less for improved data perfor - mance in com3. rxd1 polarity is inverted with respect to the line data cq1. txen 1 (pin 5): cq1 driver enable. the txen1 pin enables the line data cq1 driver in push-pull mode when pulled high. to use the driver in open-collector mode, tie txd1 high ( for pull-down mode) or low ( for pull-up mode) and drive the data signal into the txen1 pin. txd1 (pin 6): cq1 driver input. the polarity of the driver output is inverted with respect to txd1. txen2 (pin 7): q2 driver enable. the txen2 pin enables the line data q2 driver in push-pull mode when pulled high. to use the driver in open-collector mode, tie txd2 high ( for pull-down mode) or low ( for pull-up mode) and drive the data signal into the txen2 pin. txd2 (pin 8): q2 driver input. the polarity of the driver output is inverted with respect to txd2. q2 (pin 9): q2 driver output. the driver output polarity is inverted with respect to the driver input txd2. con - nect a capacitor (typically 470 pf) from q2 to ground for improved per formance. cq1 (pin 10): cq1 driver output and receiver input. the driver output polarity is inverted with respect to the driver input txd1. tie directly to the industrial line data terminal. connect a capacitor (typically 470 pf) from cq1 to ground for improved performance. l+ (pin 11): power supply input and anode of internal reverse polarity protection diode. connect to the industrial line supply terminal. the l+ pin supplies current to the lt3669s internal circuitry and must be locally bypassed with at least 4.7f. en/uvlo (pin 12): the en/uvlo pin puts the lt3669 in shutdown mode. pull the pin below 0.4 v to shut down the lt3669. the 1.5 v threshold functions as an accurate undervoltage lockout ( uvlo), preventing the regulators and transceiver from operating until the input voltage has reached the programmed level. dio (pin 13): cathode of internal reverse polarity pro- tection diode. do not use a bypass capacitor at dio. an external diode from l+ to dio can be used to improve efficiency. in this case only, a bypass capacitor is al- lowed at dio. the external diode must be chosen with a reverse-breakdown voltage higher than the expected reverse-polarity condition, and it must be robust enough to withstand the inrush current of hot plugging. gnd (pin 14, lt3669): ground in lt3669. leave this pin floating or tie the pin directly to the ground plane and the industrial line ground terminal lC. da ( pin 14, LT3669-2): diode anode in LT3669-2. connect the anode of the external catch diode ( d1 in LT3669-2's block diagram) to this pin. internal circuitry senses the current through the catch diode providing frequency foldback in extreme situations. sw (pin 15): output of the internal npn power switch. connect this pin to the inductor and boost capacitor. bst (pin 16): the bst pin provides drive voltage higher than the input voltage to the internal npn power switch. connect a capacitor ( typically 0.22f ) between bst and sw. bd ( pin 17): an integrated schottky diode is connected from bd to bst, providing the charging path for the boost capacitor. connect to the output of the switching regulator. lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
13 ldo in (pin 18): ldo power supply input. this is the collector of the ldo power npn. tie to the output of the switching regulator for maximum efficiency, or to dio. to preserve reverse-polarity protection, do not connect to l+. ldo (pin 19): low dropout linear regulator output. bypass to gnd with at least 1f of capacitance. fb ldo ( pin 20): the lt3669 regulates this pin to 0.794v. connect a feedback resistor divider tap to this pin to set the output voltage of the ldo. fb out ( pin 21): the lt3669 regulates this pin to 0.794v. connect a feedback resistor divider tap to this pin to set the output voltage of the switching regulator. rt (pin 22): sets the internal oscillator frequency. tie a resistor from rt to agnd to program the frequency. see table 2 for resistor values. agnd (pin 23): analog ground used for bandgap voltage references. connect to the ground node of the passive components connected to rt , fb out , fb ldo , ilim and cpor, and to the system ground in a star connection manner. sync (pin 24): external clock synchronization input. ground this pin to run the part using the internal oscil - lator. for external synchronization, drive the sync pin with a logic -level signal with positive and negative pulse widths of at least 80 ns. choose the rt resistor to set the lt3669 switching frequency at least 20% below the lowest synchronization input. for example, if the synchronization signal is 350khz, the rt pin should be set for 280khz. sr (pin 25): slew rate control pin. setting sr low ad - justs both cq1 and q2 drivers rising and falling times for reduced emi in com1/com2 speed mode. set sr high for edge times suitable for com3. ilim (pin 26): line driver current limit programming pin. source and sink current limits for both line drivers are programmed using this pin. tie a resistor from ilim to agnd to set the drivers output current limit. tie ilim to agnd for a 140ma current limit. cpor (pin 27): reset delay timer programming pin. connect an external capacitor ( c por ) to agnd to program a reset delay time of 0.125ms/nf. rst (pin 28): active low, open-collector logic output. after v out and v ldo rises above 92.7% of its programmed value, the reset remains asserted for the period set by the capacitor on the cpor pin. rst will also pull low if v l+ is below the internal under voltage threshold and v out or v ldo are above 1.5 v for an rst pull-up resistor of 100 k. if using the por function, connect a 10 pf capacitor between the cpor and rst pins. gnd (pin 29 exposed pad): ground. tie the exposed pad directly to the ground plane and the industrial line ground terminal. the exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the circuit printed board. it must be soldered to the circuit board for proper operation. p in func t ions lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
14 b lock diagra m l+ cq1 thsd thsd rst c/q q2 q2 q + ? + ? + ? + ? sc wake enable gnd agnd 3v ldo oscillator 250khz to 2.2mhz catch diode boost diode switch driver disable en en sync + ? + ? + ? v c clamp v c soft-start 15 19 20 25 txd1 6 26 txen2 7 txd2 sr ilim 8 cpor 27 slope comp r s q qb sw 24 sync l+ l? 9 22 rt 12 21 en/uvlo 13 dio 16 bst 17 bd 18 ldo in l c out v out 14 gnd 36692 bd1 c bst r t r1 r2 0.794v fb out fb ldo fb ldo r3 r4 low dropout linear regulator + ? enable en rst + ? 0.794v en c ldo v ldo c por rst 28 power-on reset control reference generator temperature and voltage monitoring 0.736v fb out txen1 5 wake 3 rxd1 4 sc2 2 sc1 1 c l+ 29 23 base ctrl soft start en rx 3v 0.794v 0.736v en thsd 2 3 1 4 c1 c2 11 10 slew rate control driver 1 control en q sc enable slew rate control driver 2 control wake-up detect + thsd thsd lt3669 lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
15 b lock diagra m l+ cq1 en rst c/q q2 q2 q + ? + ? + ? + ? sc wake enable gnd agnd 3v ldo oscillator 250khz to 2.2mhz boost diode switch driver disable en en sync + ? + ? + ? v c clamp v c soft-start 15 19 20 25 txd1 6 26 txen2 7 txd2 sr ilim 8 cpor 27 slope comp r s q qb sw 14 da 24 sync l+ l? 9 22 rt 12 21 en/uvlo 13 dio 16 bst 17 bd 18 ldo in l c out v out 36692 bd2 c bst d1 r t r1 r2 0.794v fb out fb ldo fb ldo r3 r4 low dropout linear regulator + ? enable en rst + ? 0.794v en c ldo v ldo c por rst 28 power-on reset control reference generator temperature and voltage monitoring 0.736v fb out txen1 5 wake 3 rxd1 4 sc2 2 sc1 1 c l+ 29 23 base ctrl soft start thsd thsd rx 3v 0.794v 0.736v en thsd 2 3 1 4 c1 c2 11 10 slew rate control driver 1 control en q sc enable thsd thsd slew rate control driver 2 control wake-up detect + LT3669-2 lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
16 ti m ing diagra m s figure 1. driver rising and falling times figure 2. driver propagation delays * v dd is the external c's supply voltage which can be taken either from the switching regulators or ldos output (v out or v ldo ) v dd 8v v l+ ? 3v 0v v l+ 3v 0v v dd 36692 f01 t df t dr cq1 q2 txd1 txd2 13v c cq cq1 q2 txd1 txd2 txen1 txen2 * 13v 8v 0v v l+ 0v v dd v dd v dd /2 v dd /2 t plhd 36692 f02 t skewd = t phld ? t plhd t phld cq1 q2 txd1 txd2 c cq cq1 q2 txd1 txd2 txen1 txen2 lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
17 ti m ing diagra m s figure 3. driver enable and disable times 36692 f03 v l+ 0v v dd v dd /2 v dd /2 v dd c cq r pu t lzd t zld 0v 3v v l+ ? 3v 8v 13v cq1 q2 cq1 q2 txen1 txen2 txd1 txd2 txen1 txen2 v l+ 0v v l+ 0v v dd v dd /2 v dd /2 t hzd t zhd cq1 q2 txen1 txen2 c cq r pd cq1 q2 txd1 txd2 txen1 txen2 lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
18 ti m ing diagra m s figure 4. receiver propagation delays figure 5. receiver detection and noise filter figure 6. power-on reset waveforms 36692 f04 0v v l+ 0v v dd 8v 13v t plhr rxd1 cq1 t phlr v dd cq1 r pu rxd1 cq1 t skewr = t phlr ? t plhr 36692 f05 0v 0v v l+ v dd v thh v thl < t bit /16 t bit > t bit /16 short glitch rejected long glitch detected rxd1 cq1 t bit 36692 f06 0v v dd v rstth v out (v ldo ) v dd /2 t uv rst t rst r pu rst por control v dd lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
19 txen1 txd1 36692 f07 0v 0v 0v v l+ v l+ v l+ v l+ 0v 0ma 500ma 100ma v dd v dd v dd v dd /2 v dd /2 v dd /2 t wu * t dwu t dwu txd1 txen1 i pd wake cq1 txd1 txen1 wake cq1 v dd /2 t lzw t hzd v l+ ? 3v v l+ ? v rqh v rql r pu r pd i pd wake cq1 txen1 txd1 wake-up detect txen1 txd1 r pu r pu i pu wake cq1 txen1 txd1 wake-up detect 0ma 500ma 100ma t wu i pu v dd /2 0v 0v 0v 0v v dd v dd v dd v dd /2 v dd /2 t lzw t lzd 3v v dd /2 v dd v dd ti m ing diagra m s figure 7. wake-up waveforms * t wu is the width of the applied wake-up pulse >t dwu lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
20 o pera t ion the lt3669/LT3669-2 is a complete industrial slave in- terface, including a switching voltage regulator, an ldo, a data transceiver with wake-up detect, a second driver and a power-on reset circuit. this set of features allows a typical industrial slave device to be built with just a sensor or actuator, the lt3669 and a microcontroller to provide the digital conversion and signal processing. the line transceiver circuitry includes a receiver that monitors the cq1 line for data and sets the output rxd1 accordingly, and a driver that drives the cq1 line controlled by inputs txen1 and txd1. additionally, a second driver controlled by inputs txen2 and txd2 drives the q2 line. both drivers share a common user-adjustable sink/source current limit ( up to 330 ma, typical) by connecting a resistor to agnd at the ilim pin. the drivers feature four modes of operation: push-pull, pull-up only, pull-down only, as well as a high impedance mode. the cq1 driver also includes a built- in wake- up pulse detect circuitry that senses when the output cq1 is forced oppo - site of its driven value for a minimum of 75 s. when this wake-up signal is detected, the wa ke output pulls low to alert the host system that a data transmission is expected. the wake output returns to high impedance again when the host acknowledges the wake-up request by executing the handshake sequence of setting the txen1 input low (receive mode) and toggling the txd1 input, or under an internal reset event. both drivers support com 1 (4.8kb/s), com 2 (38.4 kb/s) and com 3 (230.4 kb/s) communication modes. the receiver supports logic swings on the cq1 pin in accordance with the io-link communication standard. tying cq1 and q2 pins together, as well as pins txd1 and txd2 and txen1 and txen2, increases the overall current capability. the drivers are equipped with a pulsing scheme that allows them to safely drive heavy capacitive loads and incandescent bulbs. outputs sc1 and sc2 will flag if cq1 or q2 outputs are forced within 2.95 v of the opposite rail they are trying to reach. a blanking time prevents false alarms during normal output transitions. the switching regulator of the lt3669 integrates the catch diode and provides a typical conversion efficiency greater than 60% at its maximum load current of 100 ma with a standard industrial supply voltage of 24v at the l+ pin and 5v output. the LT3669-2 requires an external catch diode and provides a typical efficiency greater than 75% at its maximum load current of 300 ma. compared to a linear regulator, this drastically minimizes power dissipation in the slave device, and minimizes current draw on the in - dustrial 24 v line. the regulator features an on-chip power switch and built-in compensation, soft-start, current limit, and other support circuits required to maintain a robust, well regulated output voltage. the switching frequency is adjustable with a resistor to agnd at the rt pin to allow the circuit to be optimized either for space or efficiency, and the frequency can be synchronized to an external clock to minimize interference with signal processing circuits. a precision uvlo circuit allows the system to shut down at a user-selectable voltage. an on-chip ldo linear regulator provides a second out- put voltage at up to 150 ma. the ldo has current limit with foldback for robust performance in fault conditions. the reset output ( rst ) goes low at start-up and remains low until each regulated output is within 7.3% of its final value and the user-adjustable reset timer has expired. this ensures that the supply voltages are in regulation and stable before the signal processing circuitry is allowed to start. the reset timer is programmed with an external capacitor to agnd at the cpor pin. the lt3669 tolerates transient swings to +60 v from gnd and C60 v from l+ on the cq1 and q2 pins without damage. logic inputs txd1, txd2, txen1, txen2 and sr feature 900mv thresholds and logic input sync a 1.5 v threshold to interface easily with low voltage logic. all logic outputs (rxd1, rst , sc1 , sc2 and wake ) are open collector. lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
21 line drivers setting the current limit the lt3669 line drivers have an accurate current limit that is programmed by a resistor tied from the ilim pin to ground. table 1 lists the necessary r ilim values for desired current limits. tying the ilim pin to ground sets the default current limit of 140ma. table 1. current limit vs r ilim value current limit (ma) r ilim value (k) 70 221 90 169 130 113 170 84.5 210 68.1 250 56.2 290 48.7 330 42.2 the accurate current- limit circuit loop has a time constant of approximately 10s . additionally, high speed current- limit clamps protect the part in case of heavy loads or short- circuits. figure 8 depicts the high and low side drivers output current waveforms in a short-circuit condition. slew rate control the lt3669 line drivers feature a controlled programmable slew rate for optimum emc performance. cq1 and q2 rising and falling times can be programmed using the sr a pplica t ions i n f or m a t ion input pin and are independent of the l+ supply voltage. forcing sr below 0.4 v sets the rising/falling times to a typical value of 1.6 s/2.1s. forcing sr above 0.9 v sets these times to a typical value of 260ns/340ns. the lt3669 output drivers achieve a well controlled slew rate for a wide variety of output loads while of - fering a low residual voltage ( < 2.1v) for output load currents of up to 250 ma. in order to do so, the output drivers switch to a low residual voltage mode after a defined time once the txd signal has toggled. this time is dependent on the sr pin input level. for sr low, the drivers will enter this mode after 8.5 s; for sr high, after 1.8 s. this gives enough time for the controlled slew rate mechanism to bring the outputs to within 2.95 v from the supply rails, therefore minimizing emi during the main part of the level transition. once the timer is expired the outputs will further approach the supply rails to within 2.1 v. figure 9 depicts the output waveforms during transitions. driving heavy loads the lt3669 is equipped with a pulsing mechanism to drive heavy output loads like big capacitors and incandescent bulbs, and also protect it against output short-circuit conditions. under heavy load or output short-circuit conditions, the power dissipated in the switches may increase its local junction temperature to excessive levels if the loads were driven continuously. in order to maintain robust operation, the lt3669 output drivers use pulses of variable on-time and fixed off-time (2.2 ms typical) to cool the drivers down figure 8. current limit waveform in short-circuit figure 9. output waveforms during a transition 100s/div v txen1 5v/div 0a i cq1 0.5a/div 0a i cq1 0.5a/div 36692 f08 r ilim = 42.2k v l+ = 24v low side (shorted to l+) high side (shorted to gnd) 2s/div 0v v cq1 10v/div 0v v cq1 10v/div 36692 f09 r ilim = 42.2k v l+ = 24v sr = 0v 100 pull-down 100 pull-up lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
22 50ms/div v cq1/q2 5v/div v sc1 5v/div v sc2 5v/div 36692 f10 12v/5w bulb v l+ = 12v r ilim = 42.2k 5ms/div v cq1 1v/div v sc1 5v/div 0v 36692 f11 r ilim = 42.2k 2ms/div v txen1 5v/div v cq1 0.5v/div v sc1 5v/div 36692 f12 r ilim = 42.2k a pplica t ions i n f or m a t ion until the residual voltages approach within 2.95 v of the intended power rail, in which case the loads are driven continuously. the on-time depends on the sum of the residual voltages for the active switches ( provided that the residual voltage is higher than 2.95 v) and since their current limit is fixed, it is inversely proportional to their power dissipation. the lower the power dissipated by the switches, the longer the on-time, thus optimizing the time to drive these heavy loads fully. in order to account for the case of normal load slew rate, the internal on-time timer only increases after a blanking period dependent on the sr setting. a thermal shutdown circuit with a trigger tem - perature of 140 c ( typical) provides additional protection. short- circuit and thermal shutdown flags sc1 and sc2 a short- circuit is defined as the condition where the driver s output is within 2.95 v from the opposite targeted rail, for instance if the cq1 output is programmed to be high level ( close to v l+ ) but stays within 2.95 v from gnd. if either cq1 or q2 is short-circuited, the internal pulsing mechanism and thermal shutdown circuitry will protect the drivers. open- collector outputs sc1 and sc2 will pull low during short - circuit events on cq1 an q 2, respectively . a heavy output load can be interpreted as a short-circuit condition during the first pulses, and sc1 and sc2 outputs will flag it accordingly. this information can be used by an external microcontroller to decide whether there is a real short-circuit or a heavy load is attached to the outputs. a heavy load requires a minimum amount of time to bring the drivers output outside of the short-circuit range. by setting timers using sc1 and sc2 , a short- circuit condition can be found and the microcontroller will react accordingly (by disabling the affected driver, for example). figures 10, 11 and 12 show the behavior of the pulsing scheme when driving a light bulb, a 470 f capacitor and a short-circuit. figure 10. sc1 and sc2 outputs while driving a light bulb figure 11. sc1 output while driving 470f figure 12. sc1 output while driving a short-circuit lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
23 a pplica t ions i n f or m a t ion figure 13. sc1 and sc2 waveforms in thermal shutdown (cq1 in short-circuit, txen2 low) if the junction temperature exceeds 140c ( typical), internal circuitry will shut the line drivers off. during the thermal shutdown event, sc1 and sc2 pull low simultaneously regardless of the level of the enable inputs txen1 and txen2 ( see figure 13). this behavior can be used to distinguish between short-circuit and thermal shutdown events. in case of short-circuit events without thermal shutdown being triggered, setting txen1 and txen2 low sets outputs sc1 and sc2 to high impedance, respectively . while in short-circuit, the line drivers will pulse follow - ing the pulsing scheme described earlier. depending on the cable length and nature of the heavy load, outputs sc1 and sc2 may report false information as the voltage across the line drivers exceeds the short-circuit range for a short time due to reflections in the cable at the begin - ning of each pulse. sc1 and sc2 should then be filtered digitally or by an rc filter before further processing. the analog filter should have a time constant of at least 80s, for example, using pull-up resistors of 100k for sc 1 and sc2 with 1nf to ground. the line drivers enter the protecting pulsing mechanism independently from each other. only the driver under heavy load conditions will shut off after the defined pulsing on- time. while this driver is under overload conditions data can be sent reliably on the other driver in com 2 (sr < 0.4v) provided that it is enabled a minimum of 3 ms before the data is actually applied on its txd input. for io-link communication using the cq1 transceiver in either com2 (sr < 0.4 v) or com3 (sr > 0.9 v), ensure the q2 driver is not in a heavy load or short-circuit condition after a wake-up request is acknowledged. heavy loads on q2 can still be driven on request by an io-link master during communication by setting the cycle time long enough to allow the heavy load to be fully switched between io-link device telegrams. 500ms/div v txen1 5v/div 0v 0v 0v 0v v cq1 0.2v/div v sc1 5v/div v sc2 5v/div 36692 f13 lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
24 a pplica t ions i n f or m a t ion receiver the lt3669 line receiver input is connected to pin cq1 and its output to pin rxd1. the receivers thresholds are a nonlinear function of the voltage applied to l+, as shown in figure 14. the receiver has a noise filter that rejects pulses on the cq1 line shorter than 1/16 of the bit time, i.e., 1.63 s for sr low ( com2) and 271 ns for sr high ( com3). pulses longer than 3.5/16 for com2 and 5/16 for com3 of the bit time will be detected. pulses with duration between the mentioned time frame might be detected or rejected. figure 15 illustrates the rejection and detection bands for a positive noise glitch. figure 14. receiver thresholds vs l+ supply voltage figure 15. receiver noise rejection and detection behavior for cq1 positive glitch wake-up the lt3669s wake output can be used to flag current events on cq1 when this line is overdriven by an external device. it works in the following way: a) if txen1 is high, wake will pull low if cq1 is forced opposite to its programmed level for more than 75s. thus, if txd1 is high, the cq1 programmed level is low (less than 2.1 v from gnd) and if an external device forces cq1 to a voltage higher than 2.95 v from gnd for more than 75s, wake will pull low. similarly, if txd1 is low, the cq1 programmed level is high (higher than v l+ C 2.1 v) and if an external device forces cq1 to a voltage lower than v l+ C 2.95 v for more than 75 s, wake will pull low. l+ supply voltage (v) 0 0 receiver thresholds (v) 12 14 18 30 11.8v 9.6v io-link supply range 36692 f14 0.42 v l+ v l+ 0.52 v l+ v thh v th v thl 10 5 7.5 10 40 glitch duration 0v glitch high level undefined rejected rejected rejected detected rejected 36692 f15 v thh t bit 3.5 16 t bit 5 16 (com2) (com3) t bit 1 16 lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
25 a pplica t ions i n f or m a t ion b) if txen1 is low, wake will pull low if cq1 is forced to a voltage higher than v l+ C 2.95 v for more than 75s regardless of the txd1 level. this relies on the fact that the external device has a current sink or pull-down resistor, meaning that the default level for cq1 when txen1 is low will also be low. once wake pulls low, it will stay low until a defined handshaking sequence is applied to pin txd1 and txen1. this sequence is as follows: txen1 must be set low and txd1 toggled at least once. figures 16 a and 16 b show the handshaking mechanism after wake pulls low for txen1 high and low, respectively. the wake output returns to high impedance also after an internal reset event. note that driving heavy loads or placing an external pull- up load to l + ( in case cq1 is configured in pull-down mode) may cause wake to pull low as well, even if there is no external device driving the outputs. this could lead to false wake-up events which need to be handled by the microcontroller. real wake-up events are normally fol - lowed by an exchange of information between the slave and the external device driving the outputs ( master). a microcontroller can be programmed to react to a limited number of wake- up events. if no successful communication is established, then most likely there is no external driving device, but a heavy load or a pull-up load attached to the cq1 output and the microcontrollers reaction to wake up events may be adjusted accordingly. for example, driving a 10 f capacitive load high ( txd1 set low) will force the cq1 output below v l+ C 2.95 v for more than 75s (as shown in figure 17), thus generating a false wake- up event. similarly, configuring cq1 in pull- down mode ( txd1 high ) with an external 1 k pull-up resistor to l+ will generate a false wake-up event as soon as txen1 is set low and the cq1 output is pulled high by the external pull-up resistor for more than 75s. figure 16. wake handshaking sequence when txen1 is (a) high and (b) low for v l+ = 24v figure 17. false wake-up event when driving a 10f capacitor 20s/div v txen1 5v/div v wake 5v/div v txd1 5v/div 0a i cq1 0.2a/div 36692 f16a v ilim = 0v 20s/div v txen1 5v/div v wake 5v/div v txd1 5v/div 0v v cq1 10v/div 36692 f16b 100s/div v txen1 5v/div v wake 5v/div 0v v cq1 10v/div 36692 f17 v txd1 = 0v (a) (b) lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
26 a pplica t ions i n f or m a t ion low dropout voltage regulator (ldo) fb ldo resistor network the ldo output voltage is programmed with a resistor divider between its output and the fb ldo pin. choose the resistor values according to: r3 = r4 v ldo 0.794v ? 1 ? ? ? ? ? ? reference designators refer to the block diagram. use 1% resistors to maintain output voltage accuracy. stability and output capacitance the lt3669 ldo requires an output capacitor for stability. it is designed to be stable with most low esr capacitors (typically ceramic, tantalum or low esr electrolytic). use a minimum output capacitor of 1 f with an esr of 0.5 or less to prevent oscillations. larger values of output ca - pacitance decrease peak deviations and provide improved transient response for larger load current changes. bypass capacitors, used to decouple individual components pow - ered by the lt3669, increase the effective output capacitor value. if using ceramic capacitors, use x5r or x7r types. ldo input considerations for optimum efficiency and highest output current capabil - ity, connect the ldo input to the lowest possible available supply that guarantees a regulated output voltage, taking into account the maximum ldo dropout voltage of 750mv. if the programmed output of the switching regulator satis - fies this condition, that supply could be a good choice. other wise, if no other low supply is available, then it can be connected to the dio pin. if a bypass capacitor between ldo in and gnd is needed in this configuration, connect an external diode between l+ and dio to prevent damage on the internal reverse-polarity diode due to surge currents during hot plugging. to guarantee full reverse-polarity protection, do not connect ldo in directly to l+. ldo current-limit foldback the lt3669 ldo has a current-limit foldback circuit that limits the maximum power dissipated by the ldo pass transistor to increase its robustness. figure 18 shows the transfer function between current limit and voltage across the pass transistor. figure 18. ldo current limit foldback v ldoin ? v ldo (v) 0 0 ldo current limit (ma) 35 180 6 35 36692 f18 minimum ldo load current the lt3669 ldo requires a minimum of 175 a load current to prevent its output from rising above the programmed voltage. it is recommended to choose the feedback resis - tors to meet this requirement ( for example, r4 and r3 of 4. 42k and 14 k, respectively, for a 3.3 v output voltage). ldo minimum l+ voltage the ldos error amplifier is supplied from the l+ pin. a minimum l+ to ldo voltage difference of 4 v is required to guarantee a regulated ldo output. for instance, for an ldo programmed output voltage of 3.3 v, a minimum of 7.3v at the l+ pin would meet the requirement. lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
27 a pplica t ions i n f or m a t ion switching regulator fb out resistor network the switching regulator output voltage is programmed with a resistor divider between its output and the fb out pin. choose the resistor values according to: r1 = r2 v out 0.794v ? 1 ? ? ? ? ? ? reference designators refer to the block diagram. use 1% resistors to maintain output voltage accuracy. setting the switching frequency the lt3669 switching regulator uses a constant - frequency pwm architecture that can be programmed to switch from 250khz to 2.2 mhz by using a resistor tied from the rt pin to ground. table 2 lists the required r t values for various switching frequencies. table 2. switching frequency vs r t value switching frequency (mhz) r t value (k) 0.25 110 0.3 88.7 0.4 63.4 0.5 47.5 0.6 38.3 0.7 31.6 0.8 26.7 0.9 22.6 1.0 19.6 1.2 15.4 1.4 12.1 1.6 10.0 1.8 8.06 2.0 6.65 2.2 5.49 operating frequency trade-offs selection of the operating frequency is a trade-off between efficiency, component size, minimum dropout voltage and maximum input voltage. the advantage of high frequency operation is that smaller inductor and capacitor values may be used. the disadvantages are lower efficiency, lower maximum input voltage and higher dropout voltage. the highest acceptable switching frequency (f sw(max) ) for a given application can be calculated as follows: f sw(max) = v out + v d t on(min) ? (v l + ? v sw + v d ) where v l+ is the typical input voltage, v out is the output voltage, v d is the catch diode drop (~0.72 v in lt3669) and v sw is the internal drop from l+ to sw pins (~1.0v in lt3669 and ~1.4 v in LT3669-2 at maximum load). this equation shows that a slower switching frequency is necessary to safely accommodate a high v l+ / v out ratio. lower frequency allows lower dropout voltage. the input voltage range depends on the switching frequency because the lt3669 switch has finite minimum on- and off-times. the switch can turn off for a minimum of ~210ns, but the minimum on-time is a strong function of temperature. use the minimum switch on-time curve (see typical performance characteristics) to design for an applications maximum temperature, while adding about 30% for lt3669 part-to-part variation. the minimum and maximum duty cycles that can be achieved, taking minimum on- and off-times into account are: dc min = f sw ? t on(min) dc max = 1 C f sw ? t off(min) where f sw is the switching frequency, t on(min) is the minimum switch-on time, and t off(min) is the minimum switch-off time. these equations show that the duty cycle range increases when the switching frequency is decreased. a good choice of switching frequency allows adequate input voltage range ( see the input voltage range section) and keeps the inductor and capacitor values small. lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
28 a pplica t ions i n f or m a t ion input voltage range the minimum input voltage is determined by either the lt3669s minimum operating voltage of 7.5 v or by its maximum duty cycle ( see equation in the operating fre - quency t rade-offs section). the minimum input voltage due to duty cycle is: v l + (min) = v out + v d 1 ? f sw ? t off(min) ? v d + v sw where v l +(min) is the minimum input voltage, and t off(min) is the minimum switch-off time. note that higher switch- ing frequency will increase the minimum input voltage. if a lower dropout voltage is desired, a lower switching frequency should be used. the maximum input voltage for lt3669 applications depends on switching frequency, the absolute maximum ratings of the l+ and bst pins, and the operating mode. the lt3669 can operate continuously from input voltages up to 40 v. input voltage transients of up to 60 v are also safely withstood. however, note that if v l+ exceeds v ovlo (43v typical), the lt3669 will stop switching, allowing the output to fall out of regulation. for a given application in which the switching frequency and the output voltage are already fixed, the maximum input voltage that guarantees optimum output voltage ripple for that application can be found by applying the following expression: v l + (max) = v out + v d f sw ? t on(min) ? v d + v sw where v l+(max) is the maximum operating input voltage, v out is the output voltage, v d is the catch diode drop (~0.72v in lt3669) and v sw is the internal drop from l+ to sw pins (~1.0 v in lt3669 and ~1.4 v in LT3669-2 at maximum load), f sw is the switching frequency ( set by r t ), and t on(min) is the minimum switch-on time. note that a higher switching frequency will reduce the maximum operating input voltage. conversely, a lower switching frequency is necessary to achieve optimum operation at high input voltages. special attention must be paid when the output is in start- up, short - cir cuit, or other overload conditions. in these cases, the lt3669 tries to bring the output in regulation by driving lots of current into the output load. during these events, the inductor peak current might easily reach and even exceed the maximum current limit of the lt3669, especially in those cases where the switch already operates at minimum on-time. the circuitry monitoring the current through the catch diode prevents the switch from turning on again if the inductor valley current is above 0.2a and 0.45 a nominal values for lt3669 and LT3669-2, respectively. in these cases, the inductor peak current is therefore the maximum current limit of the lt3669 plus the additional current overshoot during the turn-off delay due to minimum on-time: i l(peak) = i sw(lim) + v l + (max) ? v outol l ? t on(min) where i l(peak) is the peak inductor current, i sw(lim) is the switch current limit (0.325 a in lt3669 and 0.65a in LT3669-2), v l+(max) is the maximum expected input voltage, l is the inductor value, t on(min) is the minimum on- time and v outol is the output voltage under the overload condition. the part is robust enough to survive prolonged operation under these conditions as long as the peak in - ductor current does not exceed 0.6 a in lt3669 and 1.3a in LT3669-2. inductor current saturation and excessive junction temperature may further limit performance. inductor selection and maximum output current a good first choice for the inductor value is: l = (v out + v d ) ? k f sw (k = 9 in lt3669, k = 3.6 in LT3669-2) where f sw is the switching frequency in mhz, v out is the output voltage, v d is the catch diode drop (~0.72 v in lt3669) and l is the inductor value in h. the inductors rms current rating must be greater than the maximum load current and its saturation current should be about 30% higher. to keep the efficiency high, the series resistance ( dcr) should be less than 0.1, and the core material should be intended for high frequency applications. table 3 lists several vendors of inductors. lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
29 a pplica t ions i n f or m a t ion table 3. inductor vendors vendor url murata www.murata.com tdk www.componenttdk.com toko www.toko.com coilcraft www.coilcraft.com sumida www.sumida.com wrth elektronik www.we-online.com coiltronics www.cooperet.com for robust operation in fault conditions ( start- up or short-circuit) and high input voltage (>30 v), choose the saturation current high enough to ensure that the inductor peak current does not exceed 0.6 a and 1.3 a for lt3669 and LT3669-2, respectively. for example, an LT3669-2 application running from an input voltage of 36 v using a 33h inductor with a saturation current of 0.8 a will toler - ate the mentioned fault conditions. the optimum inductor for a given application may differ from the one indicated by this simple design guide. a larger value inductor provides a higher maximum load cur- rent and reduces the output voltage ripple. if your load is lower than the maximum load current, then you can relax the value of the inductor and operate with higher ripple current. this allows the use of a physically smaller induc - tor, or one with a lower dcr resulting in higher efficiency. be aware that if the inductance differs from the simple rule, then the maximum load current will depend on input voltage. in addition , low inductance may result in discon- tinuous mode operation, which further reduces maximum load current. for details of maximum output current and discontinuous mode operation, see linear technologys application note 44. finally, for duty cycles greater than 50% (v out / v l+ > 0.5), a minimum inductance is required to avoid subharmonic oscillations: l min = (v out + v d ) ? k f sw (k = 6.5 in lt3669; k = 2.6 in LT3669-2) the current in the inductor is a triangle wave with an av- erage value equal to the load current. the peak inductor and switch current is: i sw(peak) = i l(peak) = i out(max) + ? i l 2 where i l(peak) is the peak inductor current, i out(max) is the maximum output load current, and i l is the induc- tor ripple current. the lt3669 limits its switch current in order to protect itself and the system from overload faults. therefore, the maximum output current that the lt3669 will deliver depends on the switch current limit, the induc - tor value and the input and output voltages. when the switch is off, the voltage across the inductor is the output voltage plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor: i l = 1 ? dc ( ) ? (v out + v d ) l ? f sw where f sw is the switching frequency of the lt3669, dc is the duty cycle and l is the value of the inductor. to maintain output regulation, the inductor peak current must be less than the switch current limit i lim which is 0.325a ( lt3669) and 0.65a ( LT3669-2) at low duty cycles and decreases to 0.24a ( lt3669) and 0.48a (LT3669-2). the maximum output current is also a function of the chosen inductor value and can be approximated by the following expression: i out(max) = i lim ? i l 2 = i lim(dc = 0) ? (1 ? 0.26 ? dc) ? i l 2 (i lim(dc = 0) = 0.325a in lt3669; i lim(dc = 0) = 0.65a in LT3669-2) choosing an inductor value so that the ripple current is small will allow a maximum output current near the switch current limit. one approach to choosing the inductor is to start with the simple rulelook at the available inductors, and choose one to meet cost or space goals. then use these equations lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
30 a pplica t ions i n f or m a t ion to check that the lt3669 will be able to deliver the required output current. note again that these equations assume that the inductor current is continuous. discontinuous operation occurs when i out is less than i l /2. input capacitor bypass the input of the lt3669 circuit with a ceramic ca - pacitor of x7r or x5r type. do not use y5v types, which have poor performance over temperature and applied voltage. a 4.7 f ceramic capacitor is adequate to bypass the lt3669 and will easily handle the ripple current. note that larger input capacitance is required when a lower switching frequency is used. if the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. this can be provided with a lower performance electrolytic capacitor. step-down regulators draw current from the input sup - ply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt3669 and to force this very high frequency switching current into a tight local loop, minimizing emi. a 4.7 f capacitor is capable of this task, but only if it is placed close to the lt3669 ( see the pcb layout section for more information). a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the lt3669. a ceramic input capacitor combined with trace or cable inductance forms a high-q ( underdamped) tank circuit. if the lt3669 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the lt3669s voltage rating. for guidance see application note 88. output capacitor and output ripple the output capacitor has two essential functions. along with the inductor, it filters the square wave generated by the lt3669 to produce the dc output. in this role, it de - termines the output ripple. additionally, low impedance at the switching frequency is important. the second function is to store energy needed to satisfy transient loads and stabilize the lt3669s control loop. ceramic capacitors have very low equivalent series resistance ( esr) and provide the best ripple performance. a good starting value is: c out = k v out ? f sw (k = 17 in lt3669; k = 43 in LT3669-2) where f sw is in mhz, and c out is the recommended output capacitance in f. use x5r or x7r types. this choice will provide low output ripple and good transient response. transient performance can be improved with a higher value capacitor if combined with a phase lead capacitor (typically 22 pf) between the output and the feedback pin (fb out ). a lower value of output capacitor can be used to save space and cost but transient performance will suffer. when choosing a capacitor, look carefully through the data sheet to find out what the actual capacitance is under operating conditions ( applied voltage and temperature). a physically larger capacitor, or one with a higher voltage rating, may be required. high performance tantalum or electrolytic capacitors can be used for the output capaci - tor. low esr is important, so choose one that is intended for use in switching regulators. the esr should be 0.05 or less. such a capacitor will be larger than a ceramic capacitor and will have a larger capacitance, because the capacitor must be large to achieve low esr. LT3669-2 diode selection the catch diode ( d1 from the LT3669-2 block diagram) conducts current only during the switch-off time. average for ward current in normal operation is i d( avg ) = i out ? (1?dc) where dc is the duty cycle. however, a diode with 1 a cur- rent rating is required for overload conditions. for inputs up to the maximum operating voltage of 40 v, use a diode with a reverse- voltage rating greater than the input voltage. if transients at the input of up to 60 v are expected, use a diode with a reverse- voltage rating only higher than the maximum ovlo of 45 v. if operating at high ambient tem - peratures, consider using a schottky with low reverse leak - age. for example, diodes, inc. sbr1u40lp or dfls160, on semiconductor mbrm140, and central semiconductor cmmsh1-60 are good choices for the catch diode. lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
31 a pplica t ions i n f or m a t ion bst and bd pin considerations capacitor c bst and the internal boost schottky diode (see the block diagram) are used to generate a boost voltage that is higher than the input voltage. in most cases a 0.1f ( lt3669) and 0.22f ( LT3669-2) capaci - tor will work well. figure 19 shows two ways to arrange the boost circuit. the bst pin must be more than 1.9v above the sw pin for best efficiency. for outputs of 2.2v and above, the standard circuit (figure 19 a) is best. for outputs between 2.2 v and 2.5 v, use a 0.22f (lt3669) and 0.47f ( LT3669-2) boost capacitor. for output volt - ages below 2.2v the boost diode can be tied to the input through pin dio to preserve reverse-polarity protection (figure 19 b), or to another external supply greater than 2.2v. however the circuit in figure?19a is more efficient because the bst pin current comes from a lower voltage source. be sure that the maximum voltage ratings of the bst and bd pins are not exceeded. the minimum operating voltage of an lt3669 applica - tion is limited by the minimum input voltage and by the maximum duty cycle as outlined previously. for proper start-up , the minimum input voltage is also limited by the boost circuit. if the input voltage is ramped slowly, or the lt3669 is turned on with its en/uvlo pin (when the output is already in regulation), then the boost capacitor may not be fully charged. because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. the minimum load generally goes to zero once the circuit has started. in many cases the discharged output capacitor will present a load to the switcher, which will allow it to start. for a given programmed output volt - age v out , the minimum input voltage that guarantees a proper start-up regardless of load current is v out + 2v. synchronization synchronizing the lt3669 oscillator to an external fre - quency can be done by connecting a square wave (with 20% to 80% duty cycle) to the sync pin. the square wave amplitude should have valleys that are below 0.5v and peaks that are above 1.5v (up to 6v). the lt3669 may be synchronized over a 300 khz to 2.2mhz range. choose the r t resistor to set the lt3669 switching frequency 20% below the lowest synchroniza- tion input . for example, if the synchronization signal will be 360 khz, choose r t for 300khz. to assure a reliable dio bst sw lt3669/ LT3669-2 bd gnd v out c bst dio 36692 f19 bst sw bd gnd l+ v l+ l+ v l+ v out c bst lt3669/ LT3669-2 figure 19. tw o circuits for generating the boost voltage (a) for v out 2.2v (b) for v out < 2.2v; v l+ < 25v lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
32 a pplica t ions i n f or m a t ion and safe operation, the lt3669 will only synchronize when the output voltage is near regulation. therefore, it is necessary to choose a large enough inductor value to supply the required output current at the frequency set by the r t resistor. see the inductor selection section for more information. it is also important to note that slope compensation is set by the r t value. to avoid subhar- monics, calculate the minimum inductor value using the frequency determined by r t . pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. figure 20 shows the recommended component placement with trace, ground plane and via locations. note that large, switched currents flow in the lt3669s l+, sw and gnd pins, the external catch diode ( LT3669-2) and the input capacitor (c l+ ). place these components, along with the inductor and output capacitor (c out ), on the same side of the circuit board, and connect them on that layer, keeping the loop they form as small as possible. all connections to gnd should be made at a common star ground point or directly to a local, unbroken ground plane underneath. the sw and bst nodes should be laid out carefully to avoid interference. if the part is synchronized externally using the sync pin, arrange this signal to avoid interference with sensitive nodes, especially fb ldo , fb out , cpor, ilim and rt . finally, keep the fb ldo , fb out , cpor, ilim and rt nodes small so that the ground traces will shield them from the sw and bst nodes. the exposed pad, pin?29, on the bottom of the package acts as a heat sink and must be soldered to the ground node. to keep thermal resistance low, extend the ground plane as much as possible and add thermal vias under and near the lt3669 to any additional ground planes within the circuit board and on the bottom side. high temperature considerations power dissipation within the lt3669 can be estimated by adding the power dissipated by the switching regulator, ldo and line drivers. the switching regulators power dis - sipation can be obtained from an efficiency measurement. the ldos power dissipation can be extracted simply by calculating the product between load current and voltage drop across the ldo pass device. the line drivers con - tribution can be calculated in a similar manner taking the product of residual voltage and load current for each driver . figure 20. a good pcb layout ensures proper, low emi operation lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
33 a pplica t ions i n f or m a t ion the last parameter to take into account is the quiescent current required to keep all circuits working properly which is about 6 ma. as an example, assume an l+ voltage of 24v, a programmed v out and v ldo voltages of 5 v and 3.3v respectively and load currents for both line drivers of 250 ma. the ldo input is connected to the switching regulator output and both switching regulator and ldo outputs are driving full load (300 ma and 150 ma, respec - tively). the total power dissipation can be estimated as: p d = 24v ? 0.006a + (5v C 3.3v) ? 0.15a + + 5v ? 0.3a ? 25% + 2 ? 1.5v ? 0.25a = 1.524w with a ja of 44 c/w, the increase in junction temperature compared to ambient will be 67c. the lt3669 protects itself against internal overheating with the help of two independent thermal shutdown circuits. one of them, with a hysteresis of 12 c, shuts only the line drivers off if the junction temperature exceeds 140 c, and pulls both sc1 and sc2 outputs low during the thermal shutdown event. the ldo and switching regulator outputs keep in regulation, allowing a c to process the event. this thermal shutdown circuit keeps the junction temperature under control in those cases where only the line drivers are under heavy load or short-circuit conditions. in case of fault conditions on the ldo or switching regulator outputs , a second thermal shutdown circuit shuts them off if the junction temperature exceeds 168 c. figure 21 depicts waveforms during a thermal shutdown event. reverse-polarity protection the lt3669 is designed to withstand 60 v between any combination of the line driver ports ( l +, cq1, q 2 and gnd). the switching regulator s power devices are powered from l+ through an integrated reverse-polarity protection diode whose cathode is also wired to the dio pin. in order to avoid damaging this diode due to surge currents during hot plugging, do not place any bypass capacitors at the dio pin ( leave it unconnected) unless an external diode is connected to bolster the integrated one. surge and esd protection considerations the lt3669 contains internal protection against esd pulses (hbm 100 pf/1.5k) of 4 kv for the interface ports (l+, cq1, q2 and gnd) and 2kv for all other pins. in order to protect the lt3669 interface ports against surge and contact/air discharge events based on the iec 61000-4-5 and iec 61000-4-2 standards, additional external protection is required. tvs diodes with break - down voltages above the maximum operating voltage of the application and clamp voltages below 60 v (for the maximum expected short - circuit current during the surge/esd event) are required. for example, for surge events of level 1, a short-circuit current of 23.8a (1kv surge source with 42 resistance in series) is defined. protecting against this surge level will also protect the part against 8 kv contact/air discharge events provided figure 21. thermal shutdown waveforms 100ms/div v ldo 5v/div 5v 3.3v 0v 0v v cq1/q2 10v/div v out 5v/div v sc1/sc2 5v/div 36692 f21 line drivers on (pulling load high) thermal shutdown event thermal shutdown shuts line drivers off lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
34 a pplica t ions i n f or m a t ion that there are bypass capacitors (>470 pf) attached to pins cq1, q2 and l+. sm6t39a or equivalent tvs clamps are recommended for io-link and most other applications with l+ operating voltages as high as 36 v. use smcj36a or equivalent tvs clamps for even higher v l+ operation. figure 22 shows the placement of the tvs diodes to protect the lt3669 against surge events applied between any combination of the line driver ports. undervoltage lockout the lt3669 undervoltage lockout circuitry monitors the input supply l+ as well as the input pin en/uvlo and disables the internal circuitry if various conditions are not met. the lt3669 en/uvlo pin voltage is internally compared to a precise 1.5 v reference and can be used as an adjust - able under voltage lockout ( see figure 23). setting this pin below the 1.5 v threshold disables the switcher, ldo and line drivers. typically, uvlo is used in situations in which the input supply is current limited, or has a relatively high source resistance. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. en/uvlo prevents the lt3669 from operating at source voltages where the problems might occur. additional circuitry monitors the l+ voltage, too, and dis- ables the line drivers if it falls below 6.5v. the switching regulator and ldo are disabled for v l+ below 6.0v . current is drawn from l+ as soon as it is above 0.65 v. setting en/uvlo low reduces the quiescent current to 1.15ma. keep the connections from the resistors to the en/uvlo pin short and ensure the interplane or surface capacitance to switching nodes is minimized. if high resistor values are used, bypass the en/uvlo pin with a 1 nf capacitor to prevent coupling problems from the switch node. output voltage monitoring the lt3669 provides power supply monitoring for microprocessor- based systems including a power- on reset (por). a precise internal voltage reference and precision por comparator circuit monitor the lt3669 ldo and switch - ing regulator output voltages. these output voltages must be above 92.7% of the programmed value for rst not to be asserted ( refer to the timing diagrams section). the lt3669 will assert rst during power-up, power-down and brownout conditions. once the output voltage rises above the rst threshold, the adjustable reset timer is started and rst is released after the reset timeout period figure 22. placement of tvs diodes figure 23. undervoltage lockout + ? 1.5v internal enable 36692 f23 lt3669/LT3669-2 en/uvlo c3 v l+ r5 r6 gnd agnd + ? l+ 36692 f22 gnd lt3669/ LT3669-2 q2 cq1 lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
35 a pplica t ions i n f or m a t ion (see figure 24). on power-down, once the output voltage drops below rst threshold, rst is held at a logic low. the reset timer is adjustable using an external capacitor. the por comparator is designed to be robust against fb out and fb ldo pin noise, which could potentially false-trigger the rst pin. the por comparator lowpass filters the first stage of the comparator. this filter integrates the output of the comparator before asserting the rst . the benefit of adding this filter is that any transients at the buck regulators output must be of sufficient magnitude and duration before it triggers a logic change in the output. this prevents spurious resets caused by output voltage transients, such as load steps or short brownout condi - tions, without sacrificing the dc reset threshold accuracy. the rst signal also resets the internal wake-up latch. a wake-up event can then only be flagged when the rst signal goes high. selecting the reset timing capacitor the reset timeout period is adjustable in order to accom - modate a variety of microprocessor applications. set the reset timeout period , ( t rst ), by connecting a capacitor, c por , between the cpor pin and ground, with value determined by: c por = t rst ? 8000 pf ms this equation is accurate for reset timeout periods of 1.0ms, or greater. to program faster timeout periods, see the reset timeout period vs capacitance graph in the typical performance characteristics section. leaving the cpor pin unconnected will generate a minimum reset timeout of approximately 22 s. maximum reset timeout is limited by the largest available low leakage capacitor. the accuracy of the timeout period will be affected by capacitor leakage ( the nominal charging current is 10 a) and capacitor tolerance. a low leakage ceramic capacitor is recommended. to prevent noise from false tripping the comparator on the cpor pin, place a 10 pf capacitor between the rst and cpor pins. the rising edge of rst coupled into the cpor pin ensures generating a clean reset signal. io-link disclaimer linear technology attempts to maintain compatibility with the io-link interface and system specifications. lt c is not a member of the io-link consortium as set forth by profibus nutzerorganisation (pno) e.v. figure 24. reset timer waveforms 5ms/div v en/uvlo 5v/div 0v 0v 0v v ldo 2v/div v out 2v/div v rst 5v/div 36692 f24 12.5ms c por = 0.1f lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
36 typical a pplica t ions 5v buck, 3.3v ldo, com2, 250ma line drivers 3.3v buck, 1.8v ldo, com2, 250ma line drivers rst sc1 sc2 wake rxd1 txen1 txd1 txen2 txd2 en/uvlo l+ q2 cq1 36692 ta02 gnd sw da bst sync sr fb out 250ma 250ma 2 3 1 4 c por 0.1f v out , i out * 5v, 300ma v out c out 22f v ldo , i ldo * 3.3v, 150ma v l+ , 7.5v to 40v transient to 60v LT3669-2 c ldo 1f l1 33h d1 r t , 38.3k r ilim , 42.2k bd r1, 53.6k r4 4.42k c1 470pf c2 470pf c l+ 4.7f rt cpor agnd fb ldo ldo ldo in ilim dio r2 10.2k r3, 14k * i out(max) is 300ma and i ldo(max) is 150ma (remaining available i out is 300ma ? i ldo ) c bst 0.22f f sw = 600khz t rst = 12.5ms l1: cdrh50d28rnp-330mc v out or v ldo reset i/o i/o i/o i/o i/o i/o i/o i/o c 100k 100k 100k 10k 10k rst sc1 sc2 wake rxd1 txen1 txd1 txen2 txd2 en/uvlo l+ q2 cq1 36692 ta03 gnd sw da bst sync sr fb out 250ma 250ma 2 3 1 4 c por 0.1f v out , i out * 3.3v, 300ma v out c out 22f v ldo , i ldo * 1.8v, 150ma v l+ , 7.5v to 40v transient to 60v LT3669-2 c ldo 1f l1 33h d1 r t , 63.4k r ilim , 42.2k bd r1, 31.6k r4 4.42k c1 470pf c2 470pf c l+ 4.7f rt cpor agnd fb ldo ldo ldo in ilim dio r2 10.2k r3, 5.62k * i out(max) is 300ma and i ldo(max) is 150ma (remaining available i out is 300ma ? i ldo ) c bst 0.22f f sw = 400khz t rst = 12.5ms l1: cdrh50d28rnp-330mc v out or v ldo reset i/o i/o i/o i/o i/o i/o i/o i/o c 100k 100k 100k 10k 10k lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
37 typical a pplica t ions 3.3v buck, 3.3v ldo, com2, 100ma line drivers rst sc1 sc2 wake rxd1 txen1 txd1 txen2 txd2 en/uvlo l+ q2 cq1 36692 ta04 gnd sw bst sync sr bd fb out 100ma 100ma 2 3 1 4 c por 0.1f v out 3.3v, 100ma c out 22f v ldo 3.3v 20ma, v l+ 30v 15ma, v l+ 40v v l+ , 7.5v to 40v transient to 60v lt3669 c ldo 1f c bst 0.1f l1 82h r t , 63.4k r1, 32.4k r4 4.42k c1 470pf c2 470pf c l+ 4.7f rt cpor agnd fb ldo ldo ldo in ilim dio r2 10.2k r3, 14k f sw = 400khz t rst = 12.5ms l1: cdrh4d22hpnp-820mc v out or v ldo reset i/o i/o i/o i/o i/o i/o i/o i/o c 100k 100k 100k 10k 10k lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
38 typical a pplica t ions 5v buck, 3.3v ldo, com2, 500ma line driver (non io-link) 36692 ta05 gnd sw da bst sync sr fb out c por 0.1f v out , i out * 5v, 300ma v out c out 22f v ldo , i ldo * 3.3v, 150ma LT3669-2 c ldo 1f f sw = 600khz t rst = 12.5ms l1: cdrh50d28rnp-330mc l1 33h d1 r t , 38.3k r ilim , 42.2k bd r1, 53.6k r4 4.42k rt cpor agnd fb ldo ldo ldo in ilim dio r2 10.2k r3, 14k c bst 0.22f v out or v ldo en/uvlo l+ q2 cq1 500ma 2 3 1 4 v l+ , 7.5v to 40v transient to 60v c1 470pf c l+ 10f * i out(max) is 300ma and i ldo(max) is 150ma (remaining available i out is 300ma ? i ldo ) rst sc1 sc2 wake rxd1 txen1 txd1 txen2 txd2 reset i/o i/o i/o i/o i/o i/o c 100k 100k 100k 10k 10k lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
39 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669
40 ? linear technology corporation 2014 lt 0514 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt3669 r ela t e d p ar t s typical a pplica t ion complete 24v 3-wire power and signaling interface (com3) to master (one of four available master ports is shown) l+1 cq1 gate1 v l 36692 ta06 up to 20 meters 24v 1/4 ltc2874 2.9v to 5.5v irq sdi sck cs sdo rxd1 txen1 txd1 i/o i/o i/o i/o i/o i/o i/o i/o c sense ? 1 sense + v dd gnd 100ma q1 100f 1f 0.1f 4.7k 10 rst sc1 sc2 wake rxd1 txen1 txd1 txen2 txd2 reset i/o i/o i/o i/o i/o i/o i/o i/o en/uvlo l+ q2 cq1 c gnd sw bst sr sync bd fb out 100ma 100ma 2 3 1 4 0.1f v out , i out * 5v, 100ma v out 10f v ldo , i ldo * 3.3v, 100ma v l+ , 7.5v to 40v transient to 60v lt3669 1f f sw = 600khz t rst = 12.5ms 0.1f 10k v out or v ldo 82h 38.3k 53.6k 4.42k 470pf 470pf 4.7f rt cpor agnd fb ldo ldo ldo in ilim dio 1f 10.2k 0.2 14k * i out(max) is 100ma and i ldo(max) is 100ma (remaining available i out is 100ma ? i ldo ) q1: fqt7n10 200ma part number description comments lt c ? 2874 quad io-link master hot swap? power controller and phy phy for 4 ports compatible with io-link inter face and system specification. operates from 8v to 34v, automatic wake-up pulse generation, 20mhz spi interface lt3502/lt3502a 40v, 500ma, 1.1mhz/2.2mhz step-down switching regulator v in : 3v to 40v, v out(min) = 0.8v, i q = 1.5ma, i sd < 1a, 2mm 2mm dfn-8 and msop-10e packages ltc 3631/ltc3631-3.3/ ltc3631-5 45v, 100ma synchronous micropower step-down dc/dc converter v in : 4.5v to 45v (60v max ), v out(min) = 0.8v, i q = 12a, i sd = 3a, 3mm 3mm dfn-8 and msop-8e packages lt3012 250ma, 4v to 80v, low dropout micropower linear regulator v in : 4v to 80v, v out : 1.24v to 60v, v do = 0.4v, i q = 40a, i sd < 1a, 4mm 3mm dfn-12 and tssop-16e packages lt3667 40v, 400ma step-down switching regulator with dual fault protected ldos buck: v in : 4.3v to 40v (60v max ), v out(min) = 1.2v, i out = 400ma; ldos: v in : 1.6v to 45v (45v max ), v out(min) = 0.8v, i out = 200ma; i q = 50 a, i sd < 1a, 3mm 5 mm qfn-24 and msop-16e packages lt3082 200ma, parallelable, single resistor, low dropout linear regulator v in : 1.2v to 40v, v out(min) = 0v, reverse-battery protection, 8-lead sot-23, 3-lead sot-223 and 3mm 3mm dfn-8 packages lt 8620 62v, 2a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a and input/output current limit/monitor v in : 3.4v to 62v, v out(min) = 0.985v, i q = 2.5a, i sd < 1a, 3mm 5mm qfn-24 and msop-16e packages lt 8610 42v, 2.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in : 3.4v to 42v, v out(min) = 0.985v, i q = 2.5a, i sd < 1a, msop-16e package lt 8611 42v, 2.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a and input/output current limit/monitor v in : 3.4v to 42v, v out(min) = 0.985v, i q = 2.5a, i sd < 1a, 3mm 5mm qfn-24 package lt 3669/lt 3669-2 3669f for more information www.linear.com/lt3669 1 4 5 2 3

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